I had a quick look at it, but while it's potentially usable for Tx it doesn't really add anything much (unless perhaps you were completely out of PIO resources), and in most cases - admittedly maybe not Mike's audio application - Rx is actually the more demanding because you have to handle everything that comes at you no matter what, while on Tx if there's a slight delay between packets then that's no big deal.the HSTX block might even be usable, at least for the tx direction, though rx would obviously become a problem then
I'm not convinced that 125Mhz Tx is in fact easily doable; if you are generating the clock then you need the PIO clock to be 250MHz; if you are making the GMII Tx clock just CLK_SYS then how do you ensure your Tx data is timed correctly to meet the setup/hold requirements?and just throwing some numbers on the wall, even GMII TX should be possible on both, its only 8bit 125mhz, which PIO could easily do
but GMII RX, is using an external 125mhz clock, and to properly recover and latch on the edges, you would need at least double that?
I haven't invested any effort in looking at how to interface GMII since the numbers I've outlined above indicate that you won't have the bus bandwidth to do anything useful with it. Just maybe if you had a Tx-mostly application that wanted slightly more than 100Mbit then you could do it, but the Rx is going to be flaky. This has long been a problem with fast ethernets on slow hosts - way back in the days of 10Mbit ethernet on ISA-bus PCs, you had the problem that the PCs could talk happily to each other but you couldn't run Sun NFS over many of the ISA bus ethernet adapters in PCs as a Sun server would send back-to-back packets larger in total than the buffer on the ISA card and the packets would be lost; re-tx didn't help as it re-sent the same packets again in the same size burst....
Back in 100Mbit land, the nice thing about RMII is that it retimes the Rx data onto a host-provided 50MHz clock, as opposed to MII which requires you to sample the Rx data asynchronously relative to a line-rate derived 25MHz clock.
Statistics: Posted by arg001 — Wed Aug 06, 2025 8:47 am