This is what I discovered in my testing last night. Based on the example in 9-2, I calculated the following with both pre-dividers as 3 and the VTPXCK_DIV as 5.Just looking at the mainline driver, I see that it changes the advertised pixel rate and link frequency when configured for 4 lanes, but I see no PLL changes. Whist it may be automagical, I'm expecting to see changes in registers 0x0300-0313, and potentially 0x0110-0147 for the MIPI timing configuration.
* PLL_VT_MPY (0x0306) should be 88, which puts the VTCK at 140.8Mhz (table shows 140.4Mhz)
* PLL_OP_MPY (0x030c) should be 91, which puts the MIPI frequency at 91Mhz (table shows 90.75Mhz)
I modified the driver with these two changes and I was able to get the camera to output at all resolutions with no black screen/artifacting, and the framerate was much more accurate. These two are going to need to be dynamically set based on the number of MIPI lanes rather than hardcoded in order to work properly.
I'm not sure if going over the values in the table is the correct approach, or if I should bump both PLL_VT_MPY and PLL_OP_MPY down 1 and be slightly below the example values. The only real guidance the datasheet gives is that the pix rate of PLL1 domain should be less than the data rate of the PLL2 domain in order for the data to always be output correctly. The datasheet also shows the max speed/lane as 755Mbps for 4-lane mode, so also not sure if there'd be any benefit to increasing to a higher speed.
Statistics: Posted by peytonicmaster — Tue Dec 31, 2024 5:01 pm