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Troubleshooting • Re: BCM2711 change UART clock

Thank you for pointing to clk-bcm2835.c, it does look like the clock is configured here.
However I am still not sure how to change it using an overlay.

For the Pi5 it seems to be easier since clock management is handled by the RP1 chip which has a dedicated section in /dts/broadcom
/rp1.dtsi

Code:

rp1_clocks: clocks@18000 {compatible = "raspberrypi,rp1-clocks";#clock-cells = <1>;reg = <0xc0 0x40018000 0x0 0x10038>;clocks = <&clk_xosc>;assigned-clocks = <&rp1_clocks RP1_PLL_SYS_CORE>,  <&rp1_clocks RP1_PLL_AUDIO_CORE>,  // RP1_PLL_VIDEO_CORE and dividers are now managed by VEC,DPI drivers  <&rp1_clocks RP1_PLL_SYS>,  <&rp1_clocks RP1_PLL_SYS_SEC>,  <&rp1_clocks RP1_PLL_AUDIO>,  <&rp1_clocks RP1_PLL_AUDIO_SEC>,  <&rp1_clocks RP1_CLK_SYS>,  <&rp1_clocks RP1_PLL_SYS_PRI_PH>,  // RP1_CLK_SLOW_SYS is used for the frequency counter (FC0)  <&rp1_clocks RP1_CLK_SLOW_SYS>,  <&rp1_clocks RP1_CLK_SDIO_TIMER>,  <&rp1_clocks RP1_CLK_SDIO_ALT_SRC>,  <&rp1_clocks RP1_CLK_ETH_TSU>;assigned-clock-rates = <1000000000>, // RP1_PLL_SYS_CORE       <1536000000>, // RP1_PLL_AUDIO_CORE       <200000000>,  // RP1_PLL_SYS       <125000000>,  // RP1_PLL_SYS_SEC       <61440000>,   // RP1_PLL_AUDIO       <192000000>,  // RP1_PLL_AUDIO_SEC       <200000000>,  // RP1_CLK_SYS       <100000000>,  // RP1_PLL_SYS_PRI_PH       // Must match the XOSC frequency       <50000000>, // RP1_CLK_SLOW_SYS       <1000000>, // RP1_CLK_SDIO_TIMER       <200000000>, // RP1_CLK_SDIO_ALT_SRC       <50000000>; // RP1_CLK_ETH_TSU};
For the BCM2711 I assume it should be done in /broadcom/bcm2711.dtsi but no rates are defined here.

I really would like to know how init_uart_clock worked but I cannot find any reference.

It should be possible to assign a different clock source to UART but knowing that init_uart_clock allowed custom clock rates, it must be possible somehow.

Statistics: Posted by p0ckin3d — Thu Nov 21, 2024 8:56 am



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