The RP2350 datasheet says potentially this:
There are not any details about the max. delay for an input signal, such as MISO. And SPI is a synchronous interface: it samples input (MISO) with the same internal clock. So, based on the given "details": MISO promised to be sampled correctly up to 70 MHz SCLK (assuming zero delays) is a wrong assumption.
It does NOT work above 25 MHz!
I see a delay for input signals (e.g. in PIO) as: greater 30ns.
This limits the max. SCLK speed where it can work. Assuming SCLK out is delayed a bit, but MISO is delayed by greater 30ns --> assume that the MISO "round trip delay" is 40ns (in relation to internal SPI SCLK, sampling the MISO signal).
==> This limits the maximum working SCLK clock to: 25 MHz (SYSCLK/6, for 150MHz SYSCLK)
"Promising" that SPI peripheral 'works' up to SYSCLK/2 would mean: the MISO (with 150 MHz SYSCLK) is not delayed by more than 14ns.
But I see that input signals like MOSI are delayed by at least 30ns!
So, the conclusion is: SPI (as synchronous, full-duplex interface) cannot work faster than: 25 MHz.
BTW:
The "owner" of the RP2350 should take the MISO input delay into account in order to provide a max. speed possible value for full-duplex SPI (OK, as simplex yes). That SPI SCLK can be generated as 70 MHz does not mean that even a SPI slave response with 70 MHz can be really received error-free with RP2350.
Assume, for a full-duplex, synchronous SPI with a Master also sampling MISO - the max. SCLK speed is limited to 25 MHz (without considering any external delays).
- a SPI Master clock can be up to SYSCLK/2
- it says: "Fsspclk(min) >= 2x Fsspclkout (max)", 12.3, page 1036
- and: "maximum peak bit rate in master mode is 70.5Mb/s" (not 75 MHz on 150 MHz SYSCLK divided by 2), 12.3, page 1036
There are not any details about the max. delay for an input signal, such as MISO. And SPI is a synchronous interface: it samples input (MISO) with the same internal clock. So, based on the given "details": MISO promised to be sampled correctly up to 70 MHz SCLK (assuming zero delays) is a wrong assumption.
It does NOT work above 25 MHz!
I see a delay for input signals (e.g. in PIO) as: greater 30ns.
This limits the max. SCLK speed where it can work. Assuming SCLK out is delayed a bit, but MISO is delayed by greater 30ns --> assume that the MISO "round trip delay" is 40ns (in relation to internal SPI SCLK, sampling the MISO signal).
==> This limits the maximum working SCLK clock to: 25 MHz (SYSCLK/6, for 150MHz SYSCLK)
"Promising" that SPI peripheral 'works' up to SYSCLK/2 would mean: the MISO (with 150 MHz SYSCLK) is not delayed by more than 14ns.
But I see that input signals like MOSI are delayed by at least 30ns!
So, the conclusion is: SPI (as synchronous, full-duplex interface) cannot work faster than: 25 MHz.
BTW:
The "owner" of the RP2350 should take the MISO input delay into account in order to provide a max. speed possible value for full-duplex SPI (OK, as simplex yes). That SPI SCLK can be generated as 70 MHz does not mean that even a SPI slave response with 70 MHz can be really received error-free with RP2350.
Assume, for a full-duplex, synchronous SPI with a Master also sampling MISO - the max. SCLK speed is limited to 25 MHz (without considering any external delays).
Statistics: Posted by tjaekel — Thu Oct 10, 2024 12:33 am