Thanks fsphil! I totally forgot to check the open issues indeed.
So the way I understand it, to get higher throughput, one would need to bundle the transfers before giving them to the DMA. Not sure if the HW of the DMA can do it alone, but I believe it should be possible to do from the core1 inside the RP1. So basically a small program running on core1 that fills a buffer in the 64kb SRAM, with data from the PIO FIFO, and then triggers the DMA transfer to host memory, or signals the host processor to trigger it. Is there any progress on making the core1 accessible without hijacking the running firmware on RP1 yet? I've found these https://github.com/MichaelBell/rp1-hacking and viewtopic.php?t=363644 which suggest no progress has been made for over 1.5 years now ...
From all this I gather that the software piolib and/or libraries and/or firmware for the PI5 / RP1 are not quite there yet ... what a shame, this would make the PI5 board uniquely qualified to cover custom high-speed I/O use cases, that otherwise require an FPGA to do ... or am I missing something? Is Raspberry Pi still working on making that happen?
Also thanks to cleverca22 for pointing out the 128bit width ... so I guess what we should expect to see then is roughly 600MBit/s / 4 ~ 15-18MByte/s, which we are still quite a bit off. I looked at the sig-rok change set, but it also only uses the same library functions and buffer setup as both fsphil and me did, or did I miss something?There seems to be an open github issue on exactly this: https://github.com/raspberrypi/utils/issues/116
So the way I understand it, to get higher throughput, one would need to bundle the transfers before giving them to the DMA. Not sure if the HW of the DMA can do it alone, but I believe it should be possible to do from the core1 inside the RP1. So basically a small program running on core1 that fills a buffer in the 64kb SRAM, with data from the PIO FIFO, and then triggers the DMA transfer to host memory, or signals the host processor to trigger it. Is there any progress on making the core1 accessible without hijacking the running firmware on RP1 yet? I've found these https://github.com/MichaelBell/rp1-hacking and viewtopic.php?t=363644 which suggest no progress has been made for over 1.5 years now ...
From all this I gather that the software piolib and/or libraries and/or firmware for the PI5 / RP1 are not quite there yet ... what a shame, this would make the PI5 board uniquely qualified to cover custom high-speed I/O use cases, that otherwise require an FPGA to do ... or am I missing something? Is Raspberry Pi still working on making that happen?
Statistics: Posted by wolfre — Sun Aug 10, 2025 9:02 am