General • Re: Raspberry Pico - Tinygo - using SVD files to program

Code:

/*RP2040 Datasheet.pdf2.10. Core Supply Regulator2.15. Clocks2.18. PLL * There are two PLLs in RP2040. They are: *   - pll_sys - Used to generate up to a 133MHz system clock *   - pll_usb - Used to generate a 48MHz USB reference clockDefault PLL configuration:                  REF     FBDIV VCO            POSTDIVPLL SYS: 12 / 1 = 12MHz * 125 = 1500MHz / 6 / 2 = 125MHzPLL USB: 12 / 1 = 12MHz * 100 = 1200MHz / 5 / 5 =  48MHz*/package mainimport ("device/rp""fmt""machine""time")func decodeVsel(vregVsel uint32) float32 {switch vregVsel {case 0x6:return 0.85case 0x7:return 0.90case 0x8:return 0.95case 0x9:return 1.00case 0xA:return 1.05case 0xB:return 1.10case 0xC:return 1.15case 0xD:return 1.20case 0xE:return 1.25case 0xF:return 1.30default:return 0.80}}func main() {machine.InitSerial()        // Initialize serial for debug outputtime.Sleep(3 * time.Second) // Sleep to catch prints on serialfmt.Printf("Raspberry Pico Overclock: \n")// --- Read VREG Register ---///////////////////////////////////vregCtrlStatus := rp.VREG_AND_CHIP_RESET.VREG.Get() // Voltage regulator control and statusfmt.Printf("Voltage Regulator Register Value: 0x%08X \n", vregCtrlStatus)vregVsel := (vregCtrlStatus >> 4) & 0xF // Voltage select bitsfmt.Printf("Voltage Select = 0x%X -> %.2f V\n", vregVsel, decodeVsel(vregVsel))// PLL SYS registers ///////////////////////////////////////////////////pllSysControlStatus := rp.PLL_SYS.CS.Get() // Control and Statusfmt.Printf("PLL SYS Control and Status: 0x%08X \n", pllSysControlStatus)pllSysPower := rp.PLL_SYS.PWR.Get() // Controls the PLL power modesfmt.Printf("Controls the PLL SYS power modes: 0x%08X \n", pllSysPower)pllSysFdbkDivisor := rp.PLL_SYS.FBDIV_INT.Get() // For XOSC=12 MHz Feedback divider min=63, max=133fmt.Printf("PLL SYS Feedback divisor: %d \n", pllSysFdbkDivisor)fmt.Printf("PLL VCO frequency: %d MHz \n", (pllSysFdbkDivisor * 12)) // Divisor * 12 MHzpllSysPostDivisor := rp.PLL_SYS.PRIM.Get() // Controls the PLL post dividers for the primary outputfmt.Printf("PLL SYS post dividers for the primary output: 0x%08X \n", pllSysPostDivisor)postDiv1 := (pllSysPostDivisor >> 16) & 0x7fmt.Printf("PLL SYS post divider 1: %d \n", postDiv1)postDiv2 := (pllSysPostDivisor >> 12) & 0x7fmt.Printf("PLL SYS post divider 2: %d \n", postDiv2)// PLL SYS = (XOSC * FedbkDivisor) / postDiv1 / postDiv2pllSysFrequency := (12 * pllSysFdbkDivisor) / postDiv1 / postDiv2fmt.Printf("PLL SYS - System Clock frequency: %d MHz \n", pllSysFrequency)}

Code:

Raspberry Pico Overclock: Voltage Regulator Register Value: 0x000010C1 Voltage Select = 0xC -> 1.15 VPLL SYS Control and Status: 0x80000001 Controls the PLL SYS power modes: 0x00000004 PLL SYS Feedback divisor: 100 PLL VCO frequency: 1200 MHz PLL SYS post dividers for the primary output: 0x00061000 PLL SYS post divider 1: 6 PLL SYS post divider 2: 1 PLL SYS - System Clock frequency: 200 MHz