This is not enough. Rules:
1. Length difference between + and - of each pair: maximum 0.25mm, better 0.15mm (which equals 1ps timing delay)
2. Length difference between any two pairs: max 50mm (normally unimportant)
3. Maximum allowed total length: 100mm, always as small as possible
4. Minimal spacing between two pairs: at least 0.5mm
5. Maximum allowed via: 2, better none at all.
6. Uninterrupted solid ground plane under all differential pairs on the entire path. If changing routing layer you also must place ground vias nearby to allow current of the reference plane to flow to the reference plane of the other routing layer.
7. Width/Spacing for 100 Ohm differential 50 Ohm single ended trace impedance (did you do your calculations for your board stackup before ordering?)...
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This is unfortunate, I did not do all of these before ordering. Is there any way to fix this from the outside? it's not a critical component for my board as I have the I/O board I can do programming on, but obviously it would be nice to have. I've considered your suggestions and am reconfiguring it for any future board orders.
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No, you would only make things worse. Just account it as training expenses.
I recommend this:
https://developer.toradex.com/carrier-b ... gn-guides/
Read the Carrier Board Design Guide.
Statistics: Posted by fchk — Fri Mar 14, 2025 7:30 am