which HW was used to measure this?JDB, thank you for your helpful reply. I haven't been able to find a canned overlay to enable hardware chip selects, and noting what you say about the Tx FIFO emptying, I would be wary of using hardware chip selects unless there was a way to force the use of DMA too.
Correct me if I am wrong, but I get the impression that the CM4 uses generic GPIO for SPI chip selects, but manages to deliver reasonable performance nonetheless. Here's an analyser trace showing the delay between chip select and SCK on the CM4: cm4_spi.jpg
Whilst the delay is not bad, it's still in the region of 8 SCK periods. That doesn't look like something that's being done in hardware - it just wouldn't make any sense to design it that way.
My point is, perhaps there is a relatively easy driver fix which would at least make the CM5 SPI performance equal to that of the CM4? Is there somewhere I can post a request to bring this to the attention of someone with the necessary expertise?
Statistics: Posted by aBUGSworstnightmare — Fri Feb 21, 2025 4:56 am