General • Re: RP2350 arm floating point support

3.6.4. Floating Point Unit
The Cortex-M33 cores on RP2350 are configured with the standard Arm single-precision floating point unit (FPU).
Coprocessor ports 10 and 11 access the FPU.

1.4.3 Floating-Point Unit
The FPU provides:
• Instructions for single-precision (C programming language float type) data-processing
operations.
• Instructions for double-precision (C double type) load and store operations.
• Combined multiply-add instructions for increased precision (Fused MAC).
• Hardware support for
◦ Conversion
◦ Addition
◦ Subtraction
◦ Multiplication with optional accumulate
◦ Division
◦ Square-root
• Hardware support for denormals and all IEEE Standard 754-2008 rounding modes.
• 32 32-bit single-precision registers or 16 64-bit double-precision registers.
• Lazy floating-point context save. Automated stacking of floating-point state is delayed until the
ISR attempts to execute a floating-point instruction. This reduces the latency to enter the ISR
and removes floating-point context save for ISRs that do not use floating-point.

6.1 About the FPU
The Cortex®-M33 FPU is an implementation of the single precision variant of the Arm®v8‑M
Floating-point extension, FPv5 architecture. It provides floating-point computation functionality
that is compliant with the ANSI/IEEE Std 754-2008, IEEE Standard for Binary Floating-Point
Arithmetic, referred to as the IEEE 754 standard.
The FPU supports all single-precision data-processing instructions and data types described in the
Arm®v8‑M Architecture Reference Manual.

6.2.1 FPU views of the register bank
The FPU provides an extension register file containing 32 single-precision registers.
The registers can be viewed as:
• Thirty-two 32-bit single-word registers, S0-S31.
• Sixteen 64-bit doubleword registers, D0-D15.
• A combination of registers from these views.
For more information about the FPU, see the Arm®v8‑M Architecture Reference Manual.

Statistics: Posted by gmx — Sun Sep 08, 2024 11:02 pm