There's a some useful info here :
https://www.youtube.com/watch?v=TGjUHChO1kM
The ADC uses its own clock so you're unlikely to be able to get cycle accurate timing.
[edit ]
I appears to be a simple SAR ADC so, If one assumes 4 cycles per operation (typical) then there are 24 'slots' to do each operation , in sequence
1 (?) to close sample gate - at a guess it just has to enable the mpx selection register to close the gate but there maybe more to it
X to charge the 1pf SAH cap.
1 to open the sample gate
12 slots will be required for the SAR , with perhaps extra cycles to allow the comparator to settle
1 or 2 to latch the output into the fifo
Given the 1pf SAH cap has to charge , allowing 8 cycles (~170nS) seems reasonable , so probably safe to switch an external mpx after 350-400nS![:-)]( "Smile")
at a guess![;-)]( "Wink")
https://www.youtube.com/watch?v=TGjUHChO1kM
The ADC uses its own clock so you're unlikely to be able to get cycle accurate timing.
[edit ]
I appears to be a simple SAR ADC so, If one assumes 4 cycles per operation (typical) then there are 24 'slots' to do each operation , in sequence
1 (?) to close sample gate - at a guess it just has to enable the mpx selection register to close the gate but there maybe more to it
X to charge the 1pf SAH cap.
1 to open the sample gate
12 slots will be required for the SAR , with perhaps extra cycles to allow the comparator to settle
1 or 2 to latch the output into the fifo
Given the 1pf SAH cap has to charge , allowing 8 cycles (~170nS) seems reasonable , so probably safe to switch an external mpx after 350-400nS
at a guess
Statistics: Posted by BillTodd — Tue Jan 30, 2024 9:30 am