

rp1_vec.c
Code:
static enum drm_mode_status rp1vec_mode_valid(struct drm_device *dev, const struct drm_display_mode *mode){int prog = !(mode->flags & DRM_MODE_FLAG_INTERLACE);int fake_31khz = prog && mode->vtotal >= 500;int vtotal_2fld = mode->vtotal << (prog && !fake_31khz);int vdisplay_2fld = mode->vdisplay << (prog && !fake_31khz);int real_clock = mode->clock >> fake_31khz;/* Check pixel clock is in the permitted range */if (real_clock < 6750)return MODE_CLOCK_LOW;else if (real_clock > 21600)return MODE_CLOCK_HIGH;/* Try to match against the 525-line 60Hz mode (System M) */if (vtotal_2fld >= 524 && vtotal_2fld <= 526 && vdisplay_2fld <= 486 && mode->htotal * vtotal_2fld > 32 * real_clock && mode->htotal * vtotal_2fld < 34 * real_clock && 37 * mode->hdisplay <= 2 * real_clock) /* 54us */return MODE_OK;/* All other supported TV Systems (625-, 405-, 819-line) are 50Hz */if (mode->htotal * vtotal_2fld > 39 * real_clock && mode->htotal * vtotal_2fld < 41 * real_clock) {if (vtotal_2fld >= 624 && vtotal_2fld <= 626 && vdisplay_2fld <= 576 && 37 * mode->hdisplay <= 2 * real_clock) /* 54us */return MODE_OK;if (vtotal_2fld == 405 && vdisplay_2fld <= 380 && 49 * mode->hdisplay <= 4 * real_clock) /* 81.6us */return MODE_OK;if (vtotal_2fld == 819 && vdisplay_2fld <= 738 && 25 * mode->hdisplay <= real_clock) /* 40us */return MODE_OK;}return MODE_BAD;}
Code:
if (mode->vtotal == 405 || mode->vtotal == 819) {/* Systems A and E (interlaced only) */vec->fake_31khz = false;mode_family = 1;hwm = &rp1vec_vintage_modes[(mode->vtotal == 819) ? 1 : 0];} else {/* 525- and 625-line modes, with half-height and "fake" progressive variants */vec->fake_31khz = mode->vtotal >= 500 && !(mode->flags & DRM_MODE_FLAG_INTERLACE);h = (mode->vtotal >= 500) ? (mode->vtotal >> 1) : mode->vtotal;if (h >= 272)mode_family = 1; /* PAL-625 */else if (tvstd == DRM_MODE_TV_MODE_PAL_M || tvstd == DRM_MODE_TV_MODE_PAL)mode_family = 2; /* PAL-525 */elsemode_family = 0; /* NTSC-525 */hwm = &rp1vec_hwmodes[mode_family][(mode->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0];}
Statistics: Posted by rTomasa — Thu May 02, 2024 1:42 am